Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

In this paper, a new low voltage MOSFET (LV MOSFET) and high dual-gate (HV DG have been proposed with concept of integration based on trench technology InGaAs material. Junction isolation technique is used for the implementation power dual gate in same epitaxial layer side by side. The HV consists that are placed drift region under oxide-filled trenches. structure minimize on-resistance (Ron) along increased breakdown (Vbr) due to enhanced RESURF effect, creation channels, folding vertical direction. MOSFET, drain current (ID) increases leading transconductance (gm) simultaneous conduction channels improved maximum oscillation frequency (fmax) cut-off (ft). On other side, centre within an oxide create two n-channels p-base. conducting parallel give substantial enhancement peak gm, ID, fmax ft more control over short channel parameters. design performance analysis carried out 2-D ATLAS device simulator.